(1) Field of the Invention
This invention relates to a method of fabrication used to form isolation regions in semiconductor devices and particularly to a method to form shallow trenches for isolation regions in semiconductor devices and more specifically to a method to form shallow trench isolation (STI).
(2) Description of Related Art
As semiconductor integrated circuits progress toward greater micro-miniaturation active devices are packed into ever smaller areas and electrical isolation between active devices becomes an extremely important issue. Shallow trenches filled with insulating material have proven to be most desirable for isolating active devices. However, the trench isolation process still suffers from a problem of sub-threshold "double-hump" in I-V characteristics caused by sharp corners at the top periphery of the isolation trench. In addition, trench isolation processes also suffer from a problem of eroded insulating material at trench edges after conventional shallow trench isolation processing. This erosion of insulating material produces "divots" at the edges of the trench and, also, worsens the abnormal device characteristics, such as the "double hump" in I-V curves, and, additionally makes subsequent gate etching more difficult. Therefore, a challenge in the industry is to provide a means of formation of planarized isolation trenches having rounded corners at the top periphery of the trenches and without the formation of "divots" at the edges of the trenches.
Numerous improvements to methods of forming planarized isolation trenches have been invented. For example, U.S. Pat. No. 5,578,518 entitled "Method of Manufacturing a Trench Isolation Having Round Corners" granted Nov. 26, 1996 to Hidetoshi Koike et al describes a method of forming shallow trench isolation which produces rounded corners on the STI.
Also, U.S. Pat. No. 5,258,332 entitled "Method of Manufacturing Semiconductor Devices Including Rounding of Corner Portions by Etching" granted Nov. 2, 1993 to Keiji Horioka et al shows methods of forming rounded STI corners using plasma etching in gas mixtures including fluorine and oxygen.
U.S. Pat. No. 5,674,775 entitled "Isolation Trench With a Rounded Top Edge Using an Etch Buffer Layer" granted Oct. 7, 1997 to Chin-Hsiung Ho et al shows a method of forming STI with rounded corners using a sacrificial spacer during etching of the trench.
U.S. Pat. No. 5,433,794 entitled "Spacers Used To Form Isolation Trenches With Improved Corners" granted Jul. 18, 1995 to Pierre C. Fazan et al describes a method of forming trench isolation in which the isolating material extends over the peripheral edge of the trench, thereby creating a small rounded cap over the trench.
U.S. Pat. No. 4,876,217 entitled "Method of Forming Semiconductor Structure Isolation Regions" granted Oct. 24, 1989 to Peter J. Zdebel describes a method of forming dielectric isolation regions in a semiconductor substrate, whereby a trench is etched in the semiconductor substrate, the trench is lined with a first dielectric layer, then filled with a second dielectric layer, followed by masking and removal of the second dielectric layer outside the trench region.
U.S. Pat. No. 5,190,889 entitled "Method of Forming Trench Isolation Structure With Germanium Silicate Filling" granted Mar. 2, 1993 to Stephen S. Poon et al describes a method of forming rounded trenches. The method uses a barrier layer liner in the trench and a germanium silicate filling material.
U.S. Pat. No. 4,994,406 entitled "Method of Fabricating Semiconductor Devices Having Deep and Shallow Isolation Structures" granted Feb. 19, 1991 to Barbara Vasquez shows a method of forming isolation structures in semiconductor substrates whereby both deep trench isolation elements and shallow dielectric isolation elements may be fabricated at variable widths.
The present invention is directed to a novel method of fabricating planarized isolation trenches, wherein sharp corners at the top periphery of the trench are eliminated and erosion of insulating material at the edges of isolation trenches is suppressed,